This invention relates to the field of integrated circuits, and more specifically to flip-flops that are utilized as memory devices in integrated circuits.
An integrated circuit (IC) typically includes a silicon semiconductor crystal, called a xe2x80x9cchipxe2x80x9d, that is mounted in a ceramic or plastic package. The chip contains numerous electronic components forming digital gates and other necessary elements. The various electronic components are interconnected inside the chip to form a digital circuit. Bonding pads on the chip are welded to external pins or other external connection structures on the ceramic or plastic package. These external connection structures are used to connect the digital circuit of the IC to a printed circuit board (PCB) or other host system structure so that the IC can receive and transmit binary signals within the host system.
A xe2x80x9csequentialxe2x80x9d IC includes a digital circuit whose operating xe2x80x9cstatexe2x80x9d at an instant in time is determined at least in part by binary information that is stored in the digital circuit. Specifically, sequential ICs typically include both xe2x80x9ccombinationalxe2x80x9d circuitry (e.g., arrays of digital gates) and memory elements. Combinational circuitry outputs binary information signals at any instant in time that are entirely dependent upon the input signals presented to the combinational circuitry at that instant. The memory elements store the binary information so that it is available, for example, for use by the combinational circuitry. In operation, a sequential IC receives binary input signals from a host system. These binary input signals, together with the binary information stored by the memory elements, determine the binary output signals transmitted from the sequential IC to the host system. The binary input signals and stored binary information also determine the conditions required for changing the binary information stored in the memory elements. Therefore, a time sequence of input signals, output signals and internal memory states determines the operating xe2x80x9cstatexe2x80x9d of the sequential IC.
xe2x80x9cSynchronousxe2x80x9d sequential ICs utilize clock signals such that all changes to the binary information stored in the memory elements takes place just after each clock signal pulse. A common memory element used in synchronous sequential ICs is referred to as a xe2x80x9cflip-flopxe2x80x9d. A static flip-flop is a circuit that can maintain a binary state indefinitely (as long as power is applied to the IC) until directed by an input signal to switch states. The flip-flop switches states in response to, for example, a rising edge of a clock signal (i.e., when the clock signal changes from xe2x80x9c0xe2x80x9d (low) to xe2x80x9c1xe2x80x9d (high)). There are several types of known flip-flops, including D, RS, JK and T type flip-flops.
FIG. 1 is a block diagram showing a portion of a flip-flop 100 that includes a data signal generation circuit 110, a clock signal generation circuit 120, a register 130, and a data signal output circuit 140. Data signal generation circuit 110 receives one or more data input signals I1, I2, I3, and generates a data signal DATA that is transmitted to a data input terminal IN of register 130. Similarly, clock signal generation circuit 120 receives one or more signals C1, C2 . . . , and generates a clock signal CLOCK that is transmitted to a clock input terminal ( greater than ) of register 130. Register 130 also includes an output terminal OUT from which a stored data signal is transmitted to data signal output circuit 140. Data signal output circuit 140 transmits a flip-flop output signal OUTPUT in response to the flip-flop output signal.
The particular circuit structures associated with the various components of a flip-flop vary depending upon the requirements of the circuit in which the flip-flop is used. For example, a single data input signal may transmitted to the input terminal of data register 130 through a data signal generation circuit 110 that is made up of an unimpeded conductive path. Conversely, multiple data input signals may be transmitted to a data signal generation circuit 110 that includes multiple logic gates that generate data signal DATA. Likewise, clock signal generation circuit may be a single conductive path transmitting a single clock input signal to the clock terminal of register 130, or may include a series of logic gates that generates the clock signal CLOCK in response to several clock input signals. Moreover, data signal output circuit 140 may include a simple conductive path, or may include one or more logic gates.
Register 130 typically stores the data signal DATA received at data input terminal IN during the rising edge of the clock signal (CLOCK) received at the clock input terminal, thereby determining the xe2x80x9csetxe2x80x9d or xe2x80x9cresetxe2x80x9d state of flip-flop 100. For example, if the data signal applied to input terminal IN is xe2x80x9c1xe2x80x9d when clock signal CLOCK transitions from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d, then flip-flop 100 is placed in a set state (i.e., the data signal xe2x80x9c1xe2x80x9d is stored in register 130 and generated at output terminal OUT). If the data signal at input terminal IN is xe2x80x9c0xe2x80x9d during the rising clock edge, then flip-flop 100 is placed in a reset state (i.e., the signal generated at output terminal OUT is xe2x80x9c0xe2x80x9d).
FIG. 2 is a timing diagram showing data signals (DATA) generated by data signal generation circuit 110 (see FIG. 1) and clock signals (CLOCK) generated by clock signal generation circuit 120. These signals are transmitted to register 130 during operation of flip-flop 100. As mentioned above, data signal generation circuit 110 and clock signal generation circuit 120 often include combinatorial circuitry and/or buffers that introduce delays in the signal transmission of the data and clock signals to the input terminals of register 130. Because flip-flop 100 is placed in a set or reset state based on the data signal DATA applied to the data input terminal IN of register 130 when the clock signal CLOCK received at the clock input terminal ( greater than ) transitions from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d, it is important for the data signal DATA to be stabilized at the data input terminal for a time period, referred to as a setup time ts, before the clock signal transition is received at the clock input terminal. For similar reasons, it is important for the data signal DATA to be stabilized at the data input terminal for a further time period, referred to as a hold time th, after the clock signal transition is received. As shown in FIG. 2, setup time ts and hold time th of flip-flop 110 define a time period during which the data signal DATA must be stabilized at xe2x80x9c0xe2x80x9d (low) or xe2x80x9c1xe2x80x9d (high). Specifically, after a time period t1 during which the data signal DATA may change between xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, setup time ts and hold time th define a time period t2 during which the data signal DATA must be stable (either xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d). When the hold time th ends (i.e., during time period t3), the data signal can again change between xe2x80x9c0xe2x80x9d (low) and xe2x80x9c1xe2x80x9d (high), as indicated in FIG. 2.
During the design and development of a synchronous sequential IC, it is important to know the setup and hold times of all flip-flops in order to maximize the operating speed. That is, the setup and hold times of each flip-flop 100 (see FIG. 1) differ depending upon the delays introduced by data signal generation circuit 110 and clock signal generation circuit 120. Because these circuits are typically different for each flip-flop of an IC, the delay associated with each flip-flop is typically different. By determining the setup and hold times for each flip-flop, the sequential IC can be optimized to minimize signal transmission delays, thereby maximizing operating speed.
FIG. 3 shows a conventional method for determining the setup time ts for a flip-flop that is utilized during the design and development of an asynchronous sequential IC. The conventional method utilizes an iterative approach to identify an optimal setup time ts. In Step 310, an initial setup time ts is selected for a flip-flop that is at a high end of an expected range of setup times. In step 320, IC operation is simulated to determine whether the initial setup time is sufficient for proper operation of the flip-flop. In Step 330, if the selected setup time is insufficient, the flip-flop will malfunction (i.e., perform improperly) during the simulation. If the flip-flop functions properly, control passes on the xe2x80x9cNxe2x80x9d (no) branch to Step 340, where the setup time ts is modified (e.g., incrementally reduced or otherwise changed in accordance with a predetermined formula). Control then passes back to Step 320, where operation is again simulated. The loop formed by Steps 320, 330 and 340 is repeated until the flip-flop malfunctions in Step 340, at which time control passes along the xe2x80x9cYxe2x80x9d branch. In accordance with the conventional method, the final setup time ts is the last value at which the flip-flop operates properly.
The conventional method for determining the hold time th is similar to the method for determining the setup time ts disclosed above and in FIG. 3.
A problem with the conventional method of determining the setup time ts and the hold time th of flip-flops is that the iterative approach typically requires twenty to thirty simulations (performed in Step 320, FIG. 3) before a minimum setup time ts or a minimum hold time th is determined. When multiplied by the number of flip-flops found on a typical sequential IC, it is clear that a significant amount of design time is spent determining flip-flop setup and hold times. Further, if the initial value (i.e., the value assigned in Step 310) is too high or too low, the iterative approach may require many more iterations, or possibly may not determine a suitable value. This further increases the IC design period.
What is needed is a method for determining the setup and hold times for flip-flops that reduces the time required to design sequential ICs.
The present invention is directed to an improved method for determining static flip-flop setup and hold times that calculates the setup and hold times using estimated timing delays associated with the transmission of data and clock signals along predetermined paths to specific nodes (gates or switches) within the flip-flops.
In accordance with the present invention, the setup time of a flip-flop is determined by calculating a difference between a first timing delay associated with the transmission of a data signal from a first external node of the flip-flop to an internal node of the flip-flop, and a second timing delay associated with the transmission of a clock signal from a second external node of the flip-flop to the internal node. Determining the first and second timing delays requires, at most, two simulations. Therefore, the method according to the first embodiment significantly reduces the amount of time required to design sequential ICs when compared to conventional methods.
Also in accordance with the present invention, the hold time is determined by calculating a difference between a first timing delay associated with the transmission of a data signal from the first external node to a third internal node of the flip-flop, and a second timing delay associated with the transmission of a clock signal from the second external node to the third internal node. As with the determination of the setup time, determining the first and second timing delays requires, at most, two simulations. Therefore, the method according to the second embodiment significantly reduces the amount of time required to design sequential ICs when compared to conventional methods.